Inflection Research

This is my second of three posts on why semiconductor solutions are converging and why this is a great opportunity for FPGAs.

The Memory wall

For well over a decade processor speed has been increasing more than memory speed, because much more R&D has been poured into logic and processor design. This is because logic (Broadcom, Xilinx, Altera) and processor designers (Intel, IBM) have far better margins than memory designers (Micron, Spansion, Samsung).

Physical Barriers

It is apparent that for servers the application performance improvement curve is flattening. Intel’s generic microprocessor architecture has overtaken many RISC processors because of the shear R&D money Intel has dumped into its x86 design and manufacturing compared to RISC makers. Even so, Intel is no longer dramatically increasing the speed of its processors.

Intel is only able to keep up with Moore’s Law by adding more processors. Inefficiencies abound from using multiple processors. Programmers are not taking full advantage of these multi-core and multi-processor machines because these machines are not offering the proper development platforms and compilers for object-oriented programmers to optimize for multi-core, multi-processor environment. Additionally managing memory in these multi-core architectures is more challenging. Moore’s law is running into an instruction set wall because the data stream is too large.

Physical barriers (like transistor leakage) are inhibiting the ability for semiconductor companies to continue keeping pace with Moore’s Law. To keep up with Moore’s Law microprocessor designers are forced to build up by adding more processors. Processor manufacturers’ ability to scale clock speed and shrink transistors is decelerating. They must now use parallelism.