Inflection Research

In the previous two posts on why semiconductor solutions are converging and why this is a great opportunity for FPGAs. I explained this was occurring because of increasing semiconductor complexity and physical barriers. Below are two new end market opportunities as a result of increased digital IC complexity and physical barriers.

FPGAs in Supercomputers

FPGA’s have moved into supercomputers as the enabler of Reconfigurable Computing. Like any change in the marketplace, reconfigurable computing also represents a risk. Companies like Stretch are creating FPGA like software configurable microprocessors, but how straight-forward will engineers find the design tools?

The architecture for a RPU (reconfigurable processor unit) system is just now becoming standardized. While FPGAs theoretically have the ability to be reprogrammed at run-time software development tools have not supported this. While some proprietary systems, such as Cray’s FPGA-augmented XD1 and SGI’s Altix with RASC option, have seen limited success it appears FPGA’s may finally be entering the standard x86 market.

FPGAs entering the IT (PC/Server) Market

The reconfigurable computing data-stream-driven model may alleviate many of the performance barriers in the existing x86 server market. As prices fall and the speed of a single processor core stabilizes it is not farfetched to see FPGA’s in desktop PC’s and cell phones. A PC manufacturer may decide to use a FPGA chip to implement common tasks such as TCP/IP processing.

Xilinx and Altera are working with Intel and AMD to plug directly into new multi-core processor’s front-side bus architecture. We may start to see PLD products for this as early as mid-2008.

Both Intel and AMD have developed their own technique to allow PLD’s to plug into the PC architecture. In June 2006, AMD announced its Torrenza program creating an interface to plug into its proprietary HyperTransport CPU bus. Not to be left behind, Intel, along with IBM and others, in September 2006 announced Geneseo an open source project creating a set of extensions to PCI Express aiming to help graphics chips and other accelerators. Geneseo proposals aim to extend Express in four general areas: fine-grained power management, locking shared memory, hints to help coherent processor handle I/O more effectively, and efficiencies for mapping virtual to physical memory.

PC and server architectures are highly standardized alleviating many of the advantages of PLDs. However, as computers take over more real-time computing functions, like processing high definition video signals, there may be more of a need to balance the inflexible speed of ASICs and the flexible sluggishness of software for x86 processors. Some examples of new real-time PC computing functions could be replacing proprietary PBX systems with generic servers running unified communications software or streaming video from a home server appliance.