Xilinx and Altera have solid software design platforms that customers use to program their chips. The dynamics of the PLD industry give the top players competitive advantages due to the platform they each have created. Each platform has built a strong moat based on the number of integrated circuit design engineers that understand it (and whose careers are based on this knowledge) and the amount of intellectual property available.
Thousands and thousands of engineers make their living because of the knowledge and expertise they have of the development platforms they use. Switching costs are high for engineers to learn new design frameworks. In addition, thousands more engineers learn Xilinx and Altera’s development tools every year in colleges in the USA, India, China, and the rest of the world.
Most PLD’s are built using Xilinx or Altera’s development platform where they can also use thousands of IP cores (re-usable intellectual property) built by Xilinx or Altera (depending on whose platform you are using) and offered for free (or nearly free). Their platforms also support 3rd part IP cores.
Each company plus dozens of third party companies build re-usable components (IP cores) that increase engineers’ efficiency. For ASICs, the largest impediment to IP reuse is verification, which can consume 70% of the development cycle. With FPGAs reuse is easier as the FPGA vendors pre-verify 3rd party vendors IP.
The success of a design platform largely depends on the quality of the IP building blocks. A huge advantage that the PLD firms have over the EDA firms is a much easier migrating path from one manufacturing process to the next. This allows IP cores to be easily rolled into the next generation architecture.
The ASIC market has struggled to embed and verify 3rd party IP. With Xilinx and Altera offering end-to-end design capabilities from design tools to IP cores, including free IP cores and a marketplace for 3rd party IP cores, they are creating an ecosystem where the customer’s have one neck to choke when problems arise. Creating an environment similar to IT departments’ migration to a single primary provider (Microsoft, Oracle, IBM, or SAP) so they can have a primary partner to lean on when issues arise.
PLD’s allow IP cores to be embedded at the software level, not in the hardware. This simplifies the process so IP can be tested and verified by the supplier on a finite number of chips since FPGA’s are a common single chip manufactured in volume by the fab; as opposed to ASIC’s whose physical design is dictated by the IP cores themselves.
A behavioral change is needed to design embedded systems and programmable chips offer a different development paradigm. The Internet and web programming could never have moved as fast as it had if websites had to be bug-free when first released, a requirement for ASICs.
Having IP that is available, certified, and supported is a necessity. Programmers on the Java EE and .Net platforms are offered thousands of tested and supported libraries. This is a basic requirement of any enterprise development platform. IP sub-systems (objects) must offer easily understandable interfaces (API’s) that allow the designer to focus only on integration and their designs differentiating factor.
A serious question mark is how can EDA vendors build an evolvable design platform incorporating IP cores that can subsist across multiple ASIC generations. FPGA’s allow the platform to be based on single chip architecture, similar to how the x86 platform enabled the emergence of the PC.
Every year more IP cores are built and more engineers learn these two companies’ platforms. It would be hard for new entrants to overcome the platform network effects that have been built by Xilinx or Altera. It would be nearly impossible for a startup PLD company to compete with this breadth of knowledge. The ability of Xilinx and Altera to build developer ecosystems may eventually trump all but the highest end digital and mixed signal chips.
